1. Field of the Invention
This invention relates generally to an apparatus and method for processing electronic image data and, more particularly, to an apparatus and method for high speed parallel processing of electronic image data using shift and add circuitry.
2. Description of the Prior Art
Electronic image processing requires that a large number of arithmetic operations be conducted on a large amount of image data in a relatively short period of time. Digitizing an electronic imaging system results in a substantial increase in the volume of image data and the complexity of arithmetic operations to be formed on such digital image data. For example, a two-dimensional image comprises hundreds of thousands of individual picture elements or pixels each of which in a digital electronic imaging processing system is represented by a binary formatted image data word. Each such digital image data word in itself comprises a plurality of binary data bits thereby further increasing the volume of electronic image data to be processed.
High speed image processors such as that disclosed in U.S. Pat. No. 4,550,437 to Kobayashi et al. entitled "Apparatus for Parallel Processing of Local Image Data", issued Oct. 29, 1985 are known in the art. This image processor relies on a high speed full parallel multiplier to accomplish a multiply and add operation in a requisite time frame. Unfortunately, the circuitry for a full parallel multiplier occupies an inordinately wide area of silicon thereby making the production of such silicon circuits quite expensive even with the advent of very large scale integrated (VLSI) technology. Moreover, this full parallel multiply technique requires that the image data being processed be recalled and stored in a memory many times during processing. Thus, even if the full parallel multiply operation is performed at a very high speed, the time required for each access of the image data by the processor nevertheless limits the overall process speed of this type of circuit. The difficulty resides in the fact that the image data simply cannot be recalled the requisite number of times fast enough from memory to be timely processed.
Therefore, it is the primary object of this invention to provide an image processing circuit for providing multiple arithmetic operations on binary formatted image data words corresponding to select picture elements of an image.
It is a further object of this invention to provide an image processing circuit for simultaneously multiplying binary formatted image data words corresponding to select picture elements of an image by a plurality of different binary formatted coefficients in a timely and efficient manner without storing and recalling image data words from memory during the multiplication.